Integrated circuits (ICs) include circuitry for electrostatic discharge (ESD) protection. Currently, ESD routing provides a low resistive path from solder bumps on the IC package down to active circuitry on the semiconductor substrate of the IC. By design, the ESD routing is unidirectional from the solder bump down to the active circuitry, or from the active circuitry to the solder bump. An ESD discharge path readily allows for mitigation and avoidance of ESD current crowding.
Some IC packages include multiple IC dies on an interposer and/or package substrate. In one technique, multiple dies are stacked on each other (referred to as stacked IC assembly). With IC stacking, one IC die is electrically and mechanically mounted to another IC die, where one of the IC dies includes through-substrate vias (TSVs), The TSVs are exposed at a backside of the respective IC die and are thus subject to ESD events similar to exposed solder bumps. It is desirable to provide ESD protection in stacked IC packages while avoiding ESD current crowding.